(a) Field of the Invention
The present invention relates to a thin film transistor (TFT) panel for a liquid crystal display (LCD) and methods for manufacturing the same.
(b) Description of the Related Art
An LCD is one of the most popular flat panel displays (FPDs). The LCD has two panels having two kinds of electrodes that generate electric fields and a liquid crystal layer interposed therebetween. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
The field-generating electrodes may be formed at each of the panels or at one of the panels. One of the panels having at least one kind of the electrodes has switching elements such as thin film transistors.
In general, a TFT array panel of an LCD includes a plurality of pixel electrodes and TFTs controlling the signals supplied to the pixel electrodes. The TFT array panel is manufactured by photolithography using a plurality of photomasks. Five or six photolithography steps have been required to complete a TFT array panel. Since the photolithography process costs a lot and takes much time, it is desirable to reduce the number of the photolithography steps.
One conventional method of manufacturing a TFT array panel using four photolithography steps is disclosed in the xe2x80x9cA TFT Manufactured by 4 Masks Process with New Photolithographyxe2x80x9d (Chang Wook Han et al., Proceedings of The 18th International Display Research Conference Asia Display 98, pp. 1109-1112, 1998. 9.28-10.1).
Meanwhile, a storage capacitor for sustaining the voltage applied to a pixel is generally provided in a TFT array panel. The storage capacitor includes a storage electrode and a portion of a pixel electrode as well as a passivation layer interposed therebetween. The storage electrode is made of the same layer as a gate wire, and the portion of the pixel electrode is formed on the passivation layer. The storage electrode is covered with a gate insulating layer, a semiconductor layer and a passivation layer, and most portion of the pixel electrode is formed directly on the substrate in Han et al. Thereby, the pixel electrode should step up the triple layers of the gate insulating layer, the semiconductor layer and the passivation layer, in order to overlap the storage electrode. It may cause a disconnection of the pixel electrode near the high step-up area.
Han et al. has a problem of forming a wide region, and it is hard to make the etch depth under the grid region to be uniform, even though a wide region is formed.
U.S. Pat. Nos. 4,231,811, 5,618,643, and 4,415,262 and Japanese patent publication No. 61-181130 and etc. which disclose similar methods as Han et al. have the same problem.
It is therefore an object of the present invention to suggest new manufacturing method of thin film transistor panels.
It is another object of the present invention to simplify the manufacturing method of a TFT array panel for an LCD, thereby reducing the manufacturing costs and increasing yield.
It is another object of the present invention to prevent current leakage problems of a TFT array panel for an LCD.
These and other objects are provided, according to the present invention, by patterning a gate insulating layer pattern having a contact hole that exposes a gate pad, along with a semiconductor layer pattern and an ohmic contact layer pattern, by etching an ohmic contact layer that is not covered by the conductor pattern having dual-layered structure, a pixel electrode and a data wire, and formed thereon, and by etching the upper conductor layer of the conductor pattern that is not covered by a passivation layer.
In a manufacturing method according to the present invention, a gate wire on an insulating substrate is formed by using a first photomask. A triple layer including a gate insulating layer pattern, a semiconductor layer pattern and an ohmic contact layer pattern on the same that covers the gate wire is formed by by using a second photomask. A conductor pattern having a double-layered structure of a lower conductor layer and an upper conductor layer is formed by using a third photomask. And the ohmic contact layer pattern that is not covered with the conductor pattern is etched out. A passivation layer is formed by using a fourth photomask and the upper conductor layer of the conductor pattern which is not covered with the passivation layer is etched.
Here, the ohmic contact layer pattern may be formed of a silicide, microcrystallized silicon or doped amorphous silicon.
The gate insulating layer pattern, the semiconductor layer pattern and the ohmic contact layer pattern may have the same shapes.
In one method, a gate insulating layer and a semiconductor layer are sequentially deposited. A silicifiable metal layer is laid on the semiconductor layer to form a silicide ohmic contact layer and is removed. Then, the ohmic contact layer, the semiconductor layer and the gate insulating layer are patterned using a third mask to form an, ohmic contact layer pattern, a semiconductor layer pattern and a gate insulating layer pattern.
In another method, a gate insulating layer and a semiconductor layer are sequentially deposited and patterned using a third mask to form a semiconductor layer pattern and a gate insulating layer pattern. The silicifiable metal layer is deposited on the semiconductor layer pattern to form an ohmic contact layer pattern of silicide, and is removed. Here, the gate wire may be made of tow layers. At this time, the lower layer may be aluminum or aluminum alloy and the upper payer may be molybdenum or molybdenum alloy. The metal layer may be chromium. Also, the lower layer may be chromium, the upper payer aluminum or aluminum alloy, and the metal layer molybdenum or molybdenum alloy.
In another method, a gate insulating layer and a semiconductor layer are sequentially deposited, and a doped amorphous silicon on the semiconductor layer is deposited and microcrystalized to form an ohmic contact layer. Then, the ohmic contact layer, the semiconductor layer and the gate insulating layer are patterned by using the third mask to form the ohmic contact layer pattern, the semiconductor layer pattern and the gate insulating layer pattern.
Furthermore, the gate insulating layer pattern, the semiconductor layer pattern and the ohmic contact layer pattern may have different shapes in the step of forming the triple layers.
In this method, a gate insulating layer, a semiconductor layer and an ohmic contact layer are sequentially deposited. Then, a photoresist layer on the ohmic contact layer is coated and developed to form a photoresist layer pattern. The photoresist pattern has a first portion, a second portion thicker than the first portion and a third portion thicker than the second portion at least. Next, the ohmic contact layer, the semiconductor layer and the gate insulating layer under the first portion are patterned to form the gate insulating layer pattern, and the ohmic contact layer and the semiconductor layer under the second portion are patterned to form the ohmic contact layer pattern and the semiconductor layer pattern.
Here, the photoresist layer is exposed and developed by using the second photomask including at least a first region, a second region and a third region having different transmittance respectively and corresponding to the first portion, the second portion and the third portion respectively. It is preferable that the photoresist layer is a positive photoresist, and the transmittance of the second region is smaller than that of the first region and is larger than that of the third region.
The second photomask includes a mask substrate and at least a mask layer formed on the mask substrate. The difference of the transmittance between the second region and the third region is controlled by forming mask layers having different transmittance levels, or by adjusting the thickness of the mask layer. Furthermore, the transmittance difference of the second photomask may be controlled by forming a slit or a lattice pattern that is smaller than the resolution of the exposure equipment used in exposure step. The photomask may include at least two pieces of substrates having at least two.
It is desirable that the lower conductor layer is made of indium tin oxide.
Here, the gate wire includes a gate line, a gate electrode that is a branch of the gate line and a gate pad connected to the gate line and transmitting a scanning signal from an external circuit to the gate line. The conductor pattern includes a data wire and a pixel electrode, and the triple layers and the passivation layer has a contact hole and a first opening respectively to connect the gate pad to the external circuit electrically.
Also, the conductor pattern further comprises a redundant gate pad that is connected to the gate pad through the contact hole, and the lower conductor layer of the redundant gate pad is exposed through the first opening.
Here, the ohmic contact layer pattern has two divided portions, and the data wire includes a data line crossing the gate line, a source electrode connected to the data line and formed on the one portion of the ohmic contact layer pattern, a drain electrode formed on the other portion of the ohmic contact layer pattern opposite of the source electrode with respect to the gate electrode and separated from the source electrode, and a data pad connected to the data line and transmitting an image signal from an external circuit to the data line. The pixel electrode is connected to the drain electrode, and the passivation layer has a second opening exposing the lower conductor layer pattern of the pixel electrode and a third opening exposing the lower conductor layer pattern of the data pad. The passivation layer may have a fourth opening exposing the part of the gate insulating layer pattern on the gate line between the neighboring data lines, and it is preferable that the semiconductor layer pattern that is not covered with the passivation layer is removed.
In another manufacturing method according the present invention, a gate wire including a gate line, a gate electrode and gate pad on an insulating substrate is formed by photolithography using a first photomask. Next, a gate insulating layer, a semiconductor layer and an ohmic contact layer are sequentially deposited on the gate wire, and the semiconductor layer and the ohmic contact layer pattern along with the gate insulating layer are patterned by photolithography using a second photomask to form a gate insulating layer pattern having a contact hole exposing the gate pad, a semiconductor layer pattern and an ohmic contact layer pattern. A conductor layer having a double-layered structure made of a lower conductor layer and an upper conductor layer is formed, and patterned by photolithography using a third photomask to form a data wire including a data line, a source electrode, a drain electrode and a data pad, a pixel electrode connected to the drain electrode, and a redundant gate pad connected to the gate pad through the contact hole. Next, the ohmic contact layer pattern exposed is etched, and a passivation layer is deposited on the substrate. Then, the passivation layer is patterned by photolithography using a fourth photomask to form a passivation layer pattern having a first opening to a third opening exposing the redundant gate pad, the data pad and the pixel electrode, respectively, and the upper conductor layer that is not covered with the passivation layer is etched.
Here, it is preferable that the third opening is larger than the pixel electrode, and the ohmic contact layer is made of silicide, microcrystalized silicon or amorphous silicon.
Also, the gate insulating layer pattern, the semiconductor layer pattern and the ohmic contact layer pattern may have shapes different from each other in the step of forming the triple layers.
In another manufacturing method according to the present invention, a gate wire including a gate line, a gate electrode and gate pad on an insulating substrate is formed, and a gate insulating layer pattern covering the gate wire is formed. A semiconductor layer pattern on the gate insulating layer pattern is formed, an ohmic contact layer pattern on the semiconductor layer pattern is formed, and a data wire including a data line, a source electrode, a drain electrode and a data pad is formed. A passivation layer is formed, and a pixel electrode connected to the drain electrode is formed. At this time, the gate insulating layer pattern is patterned by using one photoresist pattern as etch mask having the different thickness according to the portion along with the semiconductor layer pattern and the ohmic contact layer pattern.
Here, the photoresist pattern has a first portion, a second portion thicker than the first portion and a third portion thicker than the second portion, and the photoresist pattern is formed by photolithography using a photomask having a first region to a third region respectively corresponding to the first portion to the third portion and having different light transmittance.
It is preferable that the photoresist pattern is a positive photoresist layer, and the transmittance of the third region is smaller than that of the first region, and is larger than that of the second region.
The photomask includes a mask substrate and at least a mask layer that is formed on the mask substrate; and the difference of the transmittance between the second region and the third region is controlled by forming the mask layers having the different transmittance or by adjusting the thickness of the mask layer.
Also, the difference of the transmittance of the photomask is controlled by forming a slit or a lattice pattern that are smaller than the resolution of the light used in exposure step.
In another manufacturing method according to the present invention, a gate wire including a gate line, a gate electrode and gate pad, and a common wire including a common signal line and a common electrode on an insulating substrate are formed. A gate insulating layer, a semiconductor layer and an ohmic contact layer on the gate wire and the common wire are sequentially formed, and a photoresist layer on the ohmic contact layer is coated. Then, the photoresist layer is exposed and developed to form a photoresist pattern having different thickness according to the portion, and the semiconductor layer and the ohmic contact layer are patterned by using the photoresist pattern to form a semiconductor layer pattern, a first ohmic contact layer pattern, and a contact hole exposing the gate pad. Next, a conductor layer is deposited and patterned along with the first ohmic contact layer pattern to form a data wire including a data line, a source electrode, a drain electrode, a data pad and a pixel electrode, and the underlying second ohmic contact layer pattern. And a passivation layer is deposited and patterned to expose the gate pad and the data pad.
In a thin film transistor array panel for a liquid crystal display according to the present invention, a gate wire formed on the insulating substrate, including a gate line, a gate electrode connected to the gate line and a gate pad connected to the end of the gate line is formed. A gate insulating layer covering the gate wire and having a contact hole exposing the gate pad is formed. A semiconductor layer is formed on the gate insulating layer, and a data wire having a double-layered structure made of lower conductor layer and upper conductor layer, that includes a data line crossing across the gate line, a source electrode connected to the data line, a drain electrode opposite to the source electrode with respect to the gate electrode and separated from the source electrode, and a data pad connected to the data line and mainly made of the lower conductor layer. A redundant gate pad covering the gate pad through the contact hole and mainly made of the lower conductor layer is formed. And a pixel electrode connected to the drain electrode and mainly made of the lower conductor layer is formed. A passivation layer formed on the data wire, the semiconductor layer, the gate insulating layer and the substrate has a first opening through a fourth opening that exposes respectively the pixel electrode, the gate insulating layer on the gate line between the neighboring data lines, the redundant gate pad and the data pad. Here, only the upper conductor layer is interposed between the passivation layer and the lower conductor layer.
It is preferable that the boundary of the semiconductor layer concurs with the boundary of the portion where the gate insulating layer overlaps the passivation layer, and semiconductor layer patterns under the neighboring data line is separated.
It is preferable that the lower conductor layer is made of indium tin oxide or transparent conductive materials and an ohmic contact layer pattern made of suicide or microcrystalized doped amorphous silicon to reduce the contact resistivity between the semiconductor layer and the upper conductor layer is formed between the semiconductor layer and the upper conductor layer. The boundary of the ohmic contact layer concurs with the boundary of the portion where the semiconductor layer overlaps the data wire.